Conventionally, electrical elements have been integrated in a two-dimensional plane of a semiconductor substrate or a semiconductor-on-insulator substrate to form an LSI. A dimension of the element has been miniaturized for increasing a memory capacity in a semiconductor memory device, however, the miniaturization has become increasingly difficult from view point of cost and technology. Therefore, an improvement of photolithography technology is desirable. However, it is anticipated that physical properties such as a breakdown voltage or the like reach to limitation without scaling driving voltage or the like level when the miniaturization is accomplished.
Recently, various approaches have been studied for highly integrating the semiconductor memory device. For example, employing a multiple-value technique, three-dimensionally stacking memory cells disclosed in Japanese Patent Publication (Kokai) No. 2003-078044, U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885, for example, using MEMS (Micro Electro Mechanical Systems) has been studied. However, it is necessary to overcome many problems for realization the approaches mentioned above. For example, in the case of three-dimensionally stacking memory cells, processing steps in a conventional method are largely increased layer by layer to increase the cost. Further, in a seek-scan type memory device using MEMS, an area of memory storage for retaining data on one bit is fixed by thermal stability or the like so as to limit the memory density.